The present invention relates to programmable memory devices, and particularly to an improved reference system for a sense amplifier of a programmable memory device.
For ascertaining the state of an addressed cell of a matrix of memory cells, it is necessary to employ an appropriate reference system. A wealth of reference systems and sense amplifiers are known and described in the literature..sup.1 The sensing requirements of programmable memory devices (EPROMs, EEPROMs, flash EEPROMS, etc.) have some unusual features. Generally the known reference systems may be defined as static, i.e. having a constant behavior. FNT .sup.1 See, e.g., the following U.S. Patents, all of which are hereby incorporated by reference: U.S. Pat. No. 5,132,576, Sense amplifier having load device providing improved access time; U.S. Pat. No. 5,109,187, CMOS voltage reference; U.S. Pat. No. 4,965,473, Eprom low voltage sense amplifier; U.S. Pat. No. 4,908,795, Semiconductor integrated circuit device with built-in memories; U.S. Pat. No. 4,903,237, Differential sense amplifier circuit for high speed ROMS, and flash memory devices; U.S. Pat. No. 4,813,018, Nonvolatile semiconductor memory device; U.S. Pat. No. 4,807,188, Nonvolatile memory device with a high number of cycle programming endurance; U.S. Pat. No. 4,785,423, Current limited EPLD array; U.S. Pat. No. 4,783,764, Semiconductor integrated circuit device with built-in memories, and peripheral circuit which may be statically or dynamically operated; U.S. Pat. No. 4,775,958, Semiconductor memory system. These materials not only provide some indication of alternative approaches to sensing, but also provide some examples of the variety of integrated circuit contexts in which the innovative sense amplifier can be used.
It is a requisite of the reference systems for reading memory cells to permit a correct discrimination within the briefest period of time possible, i.e. to promote a quick fanning out of the current characteristics of two branches of the reference circuit, one branch comprising a cell selected for reading and the other branch comprising a reference cell. Moreover, the reference system should ensure a correct discrimination also in the presence of a reduced threshold difference between a virgin cell and a programmed cell, in order to attain a higher reliability of the sensing circuit. This latter characteristic becomes especially important in the presence of so-called marginal bits (i.e. cells in which a weak programming operation and/or a combination of marginal cell parameters has produced a programmed cell exhibiting a non-null current).
In a prior U.S. patent application No. 07/878,823 (filed on May 4, 1992 by one of the present applicants and assigned to the same assignee and hereby incorporated by reference), a modulated current, offset type and a current unbalance type sense amplifier for programmable memory cells, which employ essentially identical load elements, are described. The differential sense amplifiers have cross-coupled load elements in order to implement also an output latch for storing an extracted datum. The description contained in that prior patent application is herewith incorporated by reference in its entirety.
The disclosed innovations provide a substantially "dynamic" reference system which offers definite advantages as compared with "static" reference systems of the prior art and which may be realized in a simpler way than more traditional systems.
In the presently preferred embodiment, a dynamic reference system for a sense-amplifier is implemented by using an asymmetric pair of transistors (one twice the size of the other) in the current paths between two selected sensing lines and a source of a bias current. This asymmetry adds an offset current to the currents forced through the loads of the two sensing lines. The asymmetric transistors may be driven by the signals which are generated by a pair of cascode circuits which are normally used to drive the load-connecting switches of the sensing network, or each may be driven by the signals present on the other of the two sensing lines. This introduces a dynamic behavior of the reference system during an evaluation phase of a reading cycle which follows a first capacitance-charging phase, thus enhancing overall discrimination performances of the sense amplifier. The reference system is simple to implement and offers a number of advantages as compared to "static" reference systems of the prior art.
The dynamic reference system of the invention preferably provides the capability for reading memory cells by creating a certain offset between a current forced through a first sensing line containing a reference cell and a current forced through a second sensing line containing a memory cell selected for reading of an input network of a differential sense amplifier. Each of the two lines is preferntially provided with an essentially identical load. A first high impedance amplifying stage, usually a cascode circuit has an input connected to the first line. A second high impedance amplifying stage, usually a cascode circuit has an input connected to the second line. Each of these amplifying stages generates on a respective output node a signal which is employed for driving at least a switch connected between the respective load and a bias current source, utilizing as a reference cell, in the first sensing line of the input network a cell in a non-conducting state. The dual signals generated on the respective output nodes are exploited by the two high impedance amplifying stages, usually a cascode circuits for superimposing (by use of a pair of asymmetric transistors which are functionally connected between the switches, respectively, and the bias current source and which essentially have a different size from one another,) an offset current to bias current flowing through the loads so The permits discrimination of the state of a cell selected for reading also in case of identity of the cell with the reference cell.
Essentially, the dynamic reference system of the presently preferred embodiment requires a line of selectable reference cells all in a non-conducting state. Therefore, if the memory employs cells connected in a NOR-configuration, the reference cells will all be "programmed" cells, and if the memory employs cells connected in a NAND-configuration, all the reference cells will be in a "virgin state."
In accordance with a first embodiment of the system of the invention, the two asymmetric transistors (having different sizes from each other) may be driven through their respective control (gate) terminals, by the signal which is present on the output node of the respective cascode circuit, or, in accordance with an alternative embodiment of the invention, the two asymmetric transistors may be driven by the signal which is present at the load node of the other sensing line. Moreover, for each of these two main embodiments, the circuit may be realized in various forms, as will be more fully described later.